Ion implantation is a standard technique for introducing conductivity-altering impurities into a workpiece. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the workpiece. The energetic ions in the beam penetrate into the bulk of the workpiece material and are embedded into the crystalline lattice of the workpiece material to form a region of desired conductivity.
In order for light-emitting diodes (LEDs) to gain more of the lighting market, improvements in efficiency and manufacturing cost may be required. In many processes, etching is used to form mesas between LEDs. This etching step is one area that can be improved. Defects and dislocations in the GaN of an LED create centers for etch rate enhancement or reduction. These centers result in cavities, nano-pillars/nano-columns, roughness, or other etch imperfections. In addition, different crystal orientations result in different etch rates. Furthermore, the etch rate of GaN or other compound semiconductors may be slow or provide paths for leakage in a device.
Ion implantation may be used to amorphize or damage the defects or dislocations of a compound semiconductor, such as GaN, or some other material. The etch rate is affected if the material being etched is amorphized. FIG. 1 is a cross-sectional side view of a GaN workpiece. The workpiece 100 has a GaN layer 116 and substrate 102 composed of sapphire. A mask 103, which may be photoresist or some other hard mask, is disposed on the surface of the GaN layer 116. The distance between the top surface of the GaN layer 116 with the mask 103 to the sapphire substrate 102 may be at least 1 μm, as seen by length 115 in FIG. 1. In another example, the length 115 may be at least 10 μm. Implantation from the surface to the desired depth in GaN layer 116 may be costly and time consuming and require multi-energy implantation as high as 10 MeV and a dose as high as 1E18. This may be too slow or expensive for commercial manufacturing. Lateral straggle also may occur, which could potentially damage the material of the GaN layer 116. Furthermore, point defects and dislocations formed during GaN growth may cause defects at the bottom of any trench that is formed in the GaN layer 116. This may be at least partly due to the lattice mismatch between the GaN layer 116 and the substrate 102, which will be worse closest to the intersection of the GaN layer 116 and substrate 102. What is needed is an improved method of implanting a workpiece to improve etching.